1. Field of the Invention
The present invention relates to an insulated gate semiconductor device, and more particularly, relates to an insulated gate semiconductor device such as a bipolar transistor and a power MOSFET having an insulated gate, in which an excessive short-circuit current is controlled by suppressing a voltage rise between a gate and an emitter, which occurs when a switching operation is performed at a time of short-circuiting such as a load.
2. Description of the Related Art
In a general power electronics device for driving a motor and the like, a power semiconductor element of such as an insulated gate bipolar transistor (referred to as “IGBT” hereinafter) is mainly used as a switching element in a region where a rated voltage is 300V or more because of its characteristics. Especially, a lot of attention has been lately attracted to an insulated gate semiconductor device having a trench gate, that is, an insulated gate semiconductor device having a structure in which a gate electrode is buried in a trench formed on one main face of a semiconductor substrate. This is because an insulated gate semiconductor device can be easily miniaturized so that a degree of integration thereof can be enhanced. In recent years, an IGBT chip is improved to have a rating current in ampere to a few hundred amperes, thereby allowing a power module to be miniaturized.
FIG. 13 is a sectional view schematically showing an example of a structure of a conventional trench gate IGBT (i.e., Trench Gate Bipolar Transistor) which is referred to as “TIGBT” hereinafter. A structure and an operation of the TIGBT will be described with reference to FIG. 13.
According to a constitution shown in FIG. 13, an N+ buffer layer 102 is formed on a P+ substrate 101 which is a P collector layer, and a collector electrode 112 is formed on the other face of the P+ substrate 101. An N− semiconductor (base) layer 103 is formed on the N+ buffer layer 102, and a P base region 104 is selectively formed on the N− semiconductor layer 103 in a cell region of the TIGBT by diffusing P type impurities. N+ emitter region 105 is formed on a part or a whole of the face of the P base region 104 by selectively diffusing high-concentration N type impurities.
According to the constitution in FIG. 13, a plurality of trenches 107 are formed so as to intersect the N+ emitter regions 105 at right angles. Each trench is formed to extend from a top of the N+ emitter region 105 to a depth reaching the inside of the N− semiconductor layer 103. A trench gate electrode 110 of a MOS transistor is buried in each of the trenches 107 through a gate insulating oxide film 108. The P base region 104 which is located in the periphery of the gate electrode 110 and sandwiched between the N+ emitter region 105 and the N− semiconductor layer 103 functions as a channel region. An upper face of the gate electrode 110 is covered with an interlayer insulation film 109, and an emitter electrode 111 is formed to cover the interlayer insulation film 109.
FIG. 14 is a sectional view schematically showing a structure of a carrier stored TIGBT (i.e., Carrier Stored Trench-gate Bipolar Transistor: referred to as “CSTBT” hereinafter) which was devised by the inventors of the present invention to improve characteristics of the TIGBT. According to the CSTBT, an N− semiconductor layer, that is, a carrier stored region 113 (referred to as “CS layer” hereinafter) for storing carriers is formed between the P base region 104 and the N− semiconductor (base) layer 103.
An operation of the conventional IGBT will be described with reference to FIGS. 13 and 14. While a predetermined positive collector voltage VCE is applied between the emitter electrode 111 and the collector electrode 112, a predetermined positive gate voltage VGE is applied between the emitter electrode 111 and the gate electrode 110 to turn on the gate. At this time, the channel region of the P base region 104 is changed from P type to N type to form a channel. Then, electrons are introduced from the emitter electrode 111 to the N− semiconductor layer 103 through the channel region. Thus, a forward bias state is formed between the P+ substrate (collector) 101 and the N− semiconductor layer 103 by the introduced electrons, and holes are introduced from the P+ substrate 101. Thus, the resistance of the N− semiconductor layer 103 is largely decreased and ON resistance of the IGBT is largely decreased, so that a current capacity is increased. That is, when the (positive) holes are introduced from the P substrate 101, the resistance of the N− semiconductor layer 103 is decreased.
Next, an operation when the IGBT is turned off will be described. Referring to the constitution shown in FIGS. 13 and 14, the gate voltage VGE applied between the emitter electrode 111 and the gate electrode 110 in an ON state is made to be zero or negative (reverse bias), so that the channel region previously changed to the N type is returned to the P type region. Thus, the introduction of the electrons from from the emitter electrode 111 to the N− semiconductor layer 103 is stopped. When the introduction of the electrons is stopped, the introduction of the holes from the P+ substrate 101 is also stopped. Then, the electrons and holes stored in the N− semiconductor layer 103 (and N+ buffer layer 102) are collected into the collector electrode 112 and the emitter electrode 111, respectively, or recombined with each other and disappear.
In the case of the TIGBT shown in FIG. 13, since the MOS transistor can be miniaturized to be about 1/10 on the surface also as compared with a planar gate typed IGBT, its characteristics can be improved. In addition, according to the planar typed IGBT, a current path is formed on a surface sandwiched by P base layers and an amount of voltage drop is large at this part. In contrast, according to the above TIGBT, since the gate electrode 110 is formed so as to penetrate the P base layer 104 and there is no region which is sandwiched by the P base layers, its characteristics can be improved.
In the case of the CSTBT shown in FIG. 14, since the CS layer 113 for storing the carriers is formed under the P base region 104, the holes from the P+ substrate 101 are prevented from passing to the emitter electrode 111 and the holes are stored in the CS layer 113. As a result, the ON voltage can be further lowered as compared with the TIGBT.
However, in the case of the TIGBT shown in FIG. 13, since the cell size is reduced to be about 1/10 as compared with the planar gate, there is an advantage such that the ON voltage can be considerably lowered while there is a problem such that a gate capacity and a short-circuit current are increased. In order to solve the problem, it is proposed that the cell size is increased by increasing a pitch forming the trench gate. However, when the cell size is increased, the ON voltage is raised in the TIGBT.
Meanwhile, in the case of the CSTBT shown in FIG. 14, when the cell size is increased, the ON voltage is prevented from being increased, but there is a problem such that a withstand voltage is lowered. Especially, if the withstand voltage is lowered, a switching element receives a fatal defect, so that the above problem cannot be solved by simply increasing the cell size.
FIGS. 15 and 16 show results of dependency in variation of the withstand voltage (FIG. 15) and variation of the ON voltage (FIG. 16) when a P base interval (trench interval) is increased in the TIGBT and the CSTBT, by way of device simulation. Here, the result is shown in a case where the P base interval in the TIGBT and CSTBT is set at 3 μm and the trench interval (P base interval) is increased to 11 μm in the conventional TIGBT and the CSTBT. When the trench interval is 11 μm, the cell size is increased threefold and the gate capacity decreased to ⅓, compared to the conventional case.
From the illustrated simulation calculation result, in the TIGBT (shown by •), even when the trench interval is increased, the withstand voltage is not changed so much (FIG. 15), but the ON voltage is rapidly increased (FIG. 16). Meanwhile, in the CSTBT (shown by Δ), even when the trench interval is increased, the ON voltage is not changed so much (FIG. 16) but the withstand voltage is rapidly lowered (FIG. 15), and when the trench interval is 5 μm, the withstand voltage is less than 200V and when it is 6 μm, the withstand voltage is not more than 100V. When the trench interval is further increased, the withstand voltage becomes almost 0 V. Thus, if the trench interval is increased (that is, the cell size is increased) in order to lower the gate capacity and the short-circuit current, the ON voltage is caused to be increased (in the case of the TIGBT) or the withstand voltage is caused to be lowered (in the case of the CSTBT).
Thus, as a conventional improved type, the inventors of the present invention proposed an improved type of a constitution part in which a gate electrode 110 formed in a trench is connected to an emitter electrode 111 without varying the pitch of the trench gate, for example, as a CSTBT shown in FIG. 17 (cf. Japanese Patent Unexamined Laid-open Publication No. 2003-224278, for example). That is, according to the constitution shown in FIG. 17, the emitter electrode is connected to an upper face of a second gate electrode part 110b. 
According to the above constitution, in a cell of the second gate electrode part 110b connected to the emitter electrode, a gate voltage VGE is 0V, and this means that it is a dummy gate region which does not function as a gate. In this case, there is a merit in which a withstand voltage is not caused to be lowered while a cell size is the same as that of the conventional TIGBT and CSTBT. Note that, in the description hereinafter, the terms “gate electrode” directly connected to the emitter electrode as in the above constitution means a dummy gate region.
FIG. 18 is a graph showing a relation between the conventional CS layer concentration (relative value) and in-plane variation of threshold voltage (VGEth) (relative value).
According to the above constitution, the gate capacity and the short-circuit current can be reduced to ⅓ by connecting two trench gates out of three to the emitter electrode in the trench gates region formed in a stripe shape. This means that the gate capacity and the short-circuit current can be relatively freely selected. Thus, from the result of the above-described device simulation, it is found that the CSTBT is a considerably desired device because the ON voltage is less increased in the CSTBT although the ON voltage is increased in the TIGBT.
FIGS. 19 to 23 are schematic views showing a manufacturing flow from a formation step of the CS layer to a formation step of the trench gate in manufacturing steps of the conventional CSTBT. Hereinafter, the manufacturing steps of the CSTBT will be described with reference to FIGS. 19 to 23.
First, as shown in FIG. 19, ion implantation is selectively performed with phosphor, for example, in a step of ion implantation for forming the CS layer. Then, as shown in FIG. 20, the CS layer 113 is formed by thermal diffusion. Then, as shown in FIG. 21, ion implantation is performed with boron, for example, and thermal diffusion is performed so that the P base layer 104 is formed. Then, as shown in FIG. 22, ion implantation is selectively performed with arsenic, for example, and thermal diffusion is performed to form the N+ emitter region 105. Then, as shown in FIG. 23, after the trench 107 is formed, the gate electrode 110 of polysilicon, for example, is formed in the trench through the gate insulating oxide film 108 to form the gate region.
FIGS. 24 and 25 are graphs showing results of simulation calculations of concentration profiles at sectional positions I—I and II—II in the CSTBT provided by the above step in FIG. 23, respectively. As shown in FIGS. 24 and 25, an impurity concentration of the P base layer in the channel region is different from an impurity concentration of the P base layer in the cell center region, that is, an impurity concentration of the CS layer 113 is lower in the cell center region.
However, according to the CSTBT, as its structural characteristic point, the CS layer is provided, but it can be clear from the relation between the CS layer concentration (relative value) and the in-plane variation of the threshold voltage (VGEth) (relative value) shown in FIG. 18, that the variation of the threshold voltage (VGEth) is increased because the CS layer is additionally provided.
Meanwhile, according to the TIGBT, an impurity concentration of the N− semiconductor layer 103 is about 1.0E14 cm−3 and an impurity concentration of the P base region 104 is about 1.0E17 cm−3 at a rated voltage of about 600V. Since the P base region 104 is formed on the N− semiconductor layer 103 by ion implantation and thermal diffusion, for example, even when concentration is varied in the N− semiconductor layer, concentration variation of the P base region is hardly affected by that.
According to the CSTBT, since the P base region having an impurity concentration of about 1.0E17 cm−3 is formed on the CS layer having relatively high impurity concentration of about 1.0E17 cm−3, when the concentration of the CS layer is varied, the concentration of the P base region is also varied.
Therefore, there is a problem such that the threshold voltage (VGEth) is largely varied in the CSTBT as compared with the TIGBT. In order to prevent the variation in threshold voltage, it is necessary to improve the management of manufacturing facility. Thus, it is a major issue in the CSTBT to suppress the variation in the threshold voltage (VGEth) although there are several great advantages in the CSTBT.